Justin A. Fritz

Develops a dynamical systems framework for distinguishing AI-assisted from AI-generated creative and intellectual work. Grounded in four hand-drawn conceptual diagrams produced 2022–2023, prior to the public availability of large-scale generative AI, and in the author’s experience as a hardware engineer whose AI-assisted papers have been challenged on provenance grounds.

Four propositions: (I) human creative cognition is a knowledge state machine K_t+1 = f(K_t, θ_t, ε_t) whose trajectory constitutes authorship; (II) economic value of intellectual work derives from the rate of change of the knowledge field it induces, not static output quality; (III) generative AI is a derived state-space transformer without an independent knowledge trajectory; (IV) current AI provenance evaluation measures distributional proximity to training data — the wrong metric for the right question. The synthesis reconnects to Wiener’s cybernetics trilogy (1948–1964).

Presents a four-dimension cost model for HBM die-to-die interfaces: bandwidth efficiency, access latency, energy per operation, and area-normalized throughput. All parameters grounded in JEDEC JESD235C (HBM2e) and JESD270-4A (HBM4) timing specifications.

Central finding: graph traversal and LLM inference achieve only 34–53% bandwidth efficiency on HBM4 at 8 Gb/s. The bottleneck is t_RRD — the row-to-row activation delay — not the data bus rate. HBM4’s higher data rate paradoxically reduces random-access efficiency relative to HBM2e. Standards contribution: halving t_RRD,S from 4 to 2 cycles in the HBM5 JEDEC JC-42 specification delivers +37% effective bandwidth to graph workloads and +21% to LLM inference.

Synthesizable SystemVerilog microarchitecture for BFS traversal of CSR-encoded sparse graphs stored in HBM. 12-state AXI4 traversal FSM, 2-cycle BRAM read-modify-write visited bitmap, FIFO-based frontier queue. Single-beat row-pointer fetch eliminates a second HBM round trip per vertex.

Cycle-accurate simulation at 250 MHz with 20-cycle modeled HBM latency confirms correct BFS ordering for all vertices in 514 cycles. Throughput model converges to η ≈ 40% at realistic graph degrees, consistent with the companion HBM timing analysis. FPGA bring-up path documented for Xilinx Alveo U280; ASIC target TSMC N7 / GlobalFoundries 12LP. MIT license.